CHIPS R&D: RF Metrology for HF Transistor Models, Foundry fabrication Teledyne

Abstract Advanced semiconductor technology has led to continuous performance improvements in transistors. However, many iterations are needed to obtain optimal performance and the yield and reproducibility is incredibly poor. Furthermore, US chip makers are ill-equipped with legacy measurement techniques and underperforming models. We propose a robust path to develop and verify high-frequency transistor models: 1) new on-wafer standards and calibration, 2) precision noise measurements for transistor quality assurance, 3) improved characterizations, 4) optimal models tailored to a given technology, and 5) transistor model verification across frequency with key performance indicators. Problem Statement(s) Due to the challenges of high-frequency measurements, that includes inaccuracy in on-wafer calibration and a lack of instrumentation for transistor characterization, models are currently extracted from low-frequency measure

Estimated value

$250K - $499K

Contract type

Unknown

• NAICS334413
• PSC334413